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19-3123; Rev 1a; 9/04
KIT ATION EVALU ABLE AVAIL
Complete SDARS Receiver
Features
Integrated Receiver, Requires Only One SAW Filter Self-Contained RF AGC Loop Differential I/Q Interface Complete Integrated Frequency Generation Bias Supply for External LNAs Overcurrent Protection Low-Power Standby Mode Very Small 44-Pin Thin QFN Package
General Description
The MAX2140 complete receiver is designed for satellite digital audio radio services (SDARS). The device includes a fully monolithic VCO and only needs a SAW at the IF and a crystal to generate the reference frequency. To form a complete SDARS radio, the MAX2140 requires only a low-noise amplifier (LNA), which can be controlled by a baseband controller. The small number of external components needed makes the MAX2140based platform the lowest cost and the smallest solution for SDARS. The receiver includes a self-contained RF AGC loop and baseband-controlled IF AGC loop, effectively providing a total dynamic range of over 92dB. Channel selectivity is ensured by the SAW filter and by on-chip monolithic lowpass filters. The fractional-N PLL allows a very small frequency step, making possible the implementation of an AFC loop. Additionally, the reference is provided by an external XTAL and on-chip oscillator. A reference buffer output is also provided. A 2-wire interface (I2CTM bus compatible) programs the circuit for a wide variety of conditions, providing features such as: *Programmable gains *Lowpass filters tuning *Individual functional block shutdown The MAX2140 minimizes the requirement on the baseband controller. No compensation or calibration procedures are required. The device is available in a 7mm 7mm 44-pin thin QFN package.
VCC_FE0 1 RFIN+ 2 RFIN- 3 VCC_FE1 4 IFOUT+ 5 RF AGC - MOD
MAX2140
Ordering Information
PART MAX2140ETH TEMP RANGE -40C to +85C PIN-PACKAGE 44 Thin QFN-EP*
*EP = Exposed paddle.
Block Diagram/Pin Configuration
VCC_BE4 IF2QO+ I CA2 SDA QOUT+ 34 33 VTUNE 32 VCCREG 31 VCC_VCO 1/N PFD 1/R CHP 30 VCC_FE3 29 CPOUT 28 LOCK 27 VCC_A LPF /4/8 QUAD LPF IFIN- 11 12 VCC_BE1 13 VCC_BE2 14 VCC_BE3 15 VINANT 16 VOUTANT 17 IF2IO18 IF2II19 IF2IO+ 20 IF2II+ 21 IOUT22 IOUT+ HPF 23 VCC_XTAL HPF 26 VCC_D 25 REFOUT 24 XTAL IF2QOQOUT35 IF2QI+ 36 IF2QI38 I CA1 SCL
2 2
44
43
42
41
40
39
37
XM TUNER
MAX2140
Applications
Satellite Digital Audio Radio Services (SDARS) 2.4GHz ISM Radios
IFOUT- 6 RFAGC_C 7 VCC_FE2 8 AGCPWM 9 IFIN+ 10
I2C is a trademark of Philips Corp. Purchase of I2C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
ACTUAL SIZE
7mm x 7mm
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Complete SDARS Receiver MAX2140
ABSOLUTE MAXIMUM RATINGS
VCC_XX to GND..................................................... -0.3V to +4.3V VINANT to GND.................................................... -0.3V to +5.6V AGCPWM to GND ................................................ -0.3V to +3.0V Digital Input Current ........................................................ 10mA Maximum VSWR Without Damage ........................................ 4:1 Maximum VSWR Without Oscillations ................................... 4:1 Continuous Power Dissipation (TA = +70C) 44-Pin QFN (derate 26.31mW/C above +70C) ..... 2105mW Operating Temperature Range ..........................-40C to +85C Junction Temperature .....................................................+150C Theta JC ..........................................................................12C/W Storage Temperature Range ............................-65C to +150C Lead Temperature (soldering, 10s) ................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.1V to 3.6V; VINANT VCC, VOUTANT in open circuit, TA = -40C to +85C. Typical values are at VCC = 3.3V, VINANT = 3.3V, and TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER Supply Voltage Range (Note 2) Operating Supply Current Lock Indicator High (Locked) Lock Indicator Low (Unlocked) Digital Input-Logic High Digital Input-Logic Low Input Current for Digital Control Pins Input Current for AGCPWM Voltage Drop VINANT to VOUTANT in Normal Operating Mode Current Sink at VOUTANT to Flag Bit ACP = 1 Current Sink at VOUTANT to Flag Bit AND = 1 SYMBOL VCC VINANT ICC ISHDN VIH_LK VIL_LK VIH VIL IDIG IAGCPWM VANTDCDROP
CONDITIONS
MIN 3.1 3.1
TYP 3.3 3.3 150 30
MAX 3.6 5.3 180
UNITS V mA A V
All blocks on All blocks off VCC - 0.5
0.5 VCC - 0.5 0.5 -1 -10 Maximum current sink at VOUTANT is 150mA VOUTANT shorted to ground 195 12 20 +1 +290 0.35
V V V A A V
IANTDC_H IANTDC_L
700 30
mA mA
2
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Complete SDARS Receiver
AC ELECTRICAL CHARACTERISTICS
(MAX2140 EV kit, current drawn at VOUTANT, IVOUTANT = 150mA max, VCC = 3.1V to 3.6V, VINANT = 3.1V to 5.3V, fRF = 2320MHz to 2345MHz, fLO = 2076MHz, TA = -40C to +85C. Typical values are at VCC = VINANT = 3.3V, fRF = 2338MHz, TA = +25C, unless otherwise noted.) (Note 2) Interstage (IF) 259MHz SAW filter specification: insertion loss = 19dB max, 9.3MHz to 12MHz from center attenuation = 24dB min, beyond 12MHz from center attenuation = 40dB min.
PARAMETER GENERAL RECEIVER Minimum Input RF Power to Produce 20mVP-P (Differential) at I and Q Baseband Outputs Maximum Input RF Power to Produce 400mVP-P (Differential) at I and Q Baseband Outputs LO to RF Input Leakage Noise Figure (Notes 3, 5) In-Band Input IP3 (Notes 5, 6) Out-of-Band Input IP3 (Notes 5, 7) In-Band Input IP2 (Notes 5, 6) Out-of-Band Input IP2 (Notes 5, 7) Opposite Sideband Rejection Image Rejection Half IF Rejection RF AGC LOOP LNA Gain Reduction Minimum RF AGC Trip Point RF AGC Trip Point Maximum RF AGC Trip Point FE Programmable Gain Range FE Programmable Gain Step IF FILTER INTERFACE IF Output Differential Admittance Input Differential Impedance Presented by the IC to the IF Filter Output Yout, IF Between pins IFOUT+, IFOUT-, fIF = 259MHz and 467MHz Between pins IFOUT+, IFOUT-, fIF = 259MHz and 467MHz 1/900 + j0 150 + j0 S RFAGC_ Range (Note 4) 30 42 -35 -37 -33 -15 19 22 2 26 -29 dB dBm dBm dBm dB dB PMIN IF AGC is set at maximum gain, bit HPF = 0 (Note 4) RF AGC threshold: RF_AGC_TRIP = -17dBm; IF AGC is set at minimum gain, bit HPF = 0 LO-related spurious > 2GHz LO-related spurious < 2GHz RF AGC is at maximum gain, IF AGC is at reference gain RF AGC is at maximum gain, IF AGC is at reference gain RF AGC is at maximum gain, IF AGC is at reference gain RF AGC is at maximum gain, IF AGC is at reference gain RF AGC is at maximum gain, IF AGC is at reference gain Baseband frequencies = 100kHz (Note 4) At fLO - fIF At fLO + 0.5 x fIF 32 -91 -84 dBm SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX2140
PMAX PLK_H PLK_L NF I_IIP3 O_IIP3 I_IIP2 O_IIP2 OSR IRej HRej
+3 -66 -38 8.5 -32 -9 +1 +38 39 54 53 10.4
dBm
dBm dB dBm dBm dBm dBm dB dB dB
RFAGC_mi Bits RF4/3/2/1/0 = 00000 (BIN) RFAGC_int Bits RF4/3/2/1/0 = 00010 (BIN) (Note 4) RFAGC_m FE_Rge FE_Step Bits RF4/3/2/1/0 = 10100 (BIN) (Note 4)
FRONT-END (FE) PROGRAMMABLE GAIN
Zin, IF
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Complete SDARS Receiver MAX2140
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX2140 EV kit, current drawn at VOUTANT, IVOUTANT = 150mA max, VCC = 3.1V to 3.6V, VINANT = 3.1V to 5.3V, fRF = 2320MHz to 2345MHz, fLO = 2076MHz, TA = -40C to +85C. Typical values are at VCC = VINANT = 3.3V, fRF = 2338MHz, TA = +25C, unless otherwise noted.) (Note 2) Interstage (IF) 259MHz SAW filter specification: insertion loss = 19dB max, 9.3MHz to 12MHz from center attenuation = 24dB min, beyond 12MHz from center attenuation = 40dB min.
PARAMETER IF AGC LOOP IF AGC Control Voltage for Max Gain IF AGC Control Voltage for Min Gain IF AGC Gain-Control Range IFAGC_VM Applied at pin AGCPWM IFAGC_Vm Applied at pin AGCPWM IFAGC_ Rge (Note 4) 47 0.2 2.5 64 V V dB SYMBOL CONDITIONS MIN TYP MAX UNITS
INTERNAL BASEBAND LOWPASS FILTERS LPF In-Band Ripple LPFA_rip LPFrej LPF Out-of-Band Rejection (Note 4) LPFrej INTERNAL OUTPUT STAGE Gain Increase Maximum I/QOUT Pin Loading BB_DG IQ_load VCO_ Range VCO_Gain VCO_PN VCO_jit VCHP ICHP CHP_leak PLLref PLLstep Programmable through I2C Bit CHP = 0 Bit CHP = 1 Across VCHP range 1 23 From bit HPF = 0 to HPF = 1 Per each of the four pins 4 10//10 dB k//pF From 0 to 6.3MHz with respect to the amplitude at 100kHz At 10.25MHz with respect to the amplitude at 2MHz At 16MHz with respect to the amplitude at 2MHz 14 47 0.7 21 dB 51 dB
FREQUENCY GENERATION: VCO AND PLL VCO Frequency Range VCO Tuning Gain Synthesized VCO Phase Noise Synthesized VCO Phase-Noise Jitter Charge-Pump Voltage Range Charge-Pump Current Pin CHP Leakage Current PLL Reference Division Ratio Synthesized VCO Smallest Fractional Step Over VCHP range (Note 4) (Note 4) At 10kHz outside PLL band Integrated from 100Hz to 100kHz, LO frequency = 2079MHz 0.40 0.6 1.2 5 2 Hz -80 1.2 2.75 1861 2079 240 MHz MHz/V dBc/Hz DegRMS V mA nA
4
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Complete SDARS Receiver
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX2140 EV kit, current drawn at VOUTANT, IVOUTANT = 150mA max, VCC = 3.1V to 3.6V, VINANT = 3.1V to 5.3V, fRF = 2320MHz to 2345MHz, fLO = 2076MHz, TA = -40C to +85C. Typical values are at VCC = VINANT = 3.3V, fRF = 2338MHz, TA = +25C, unless otherwise noted.) (Note 2) Interstage (IF) 259MHz SAW filter specification: insertion loss = 19dB max, 9.3MHz to 12MHz from center attenuation = 24dB min, beyond 12MHz from center attenuation = 40dB min.
PARAMETER Synthesized VCO Spurs XTAL Oscillator Frequency Range XTAL Oscillator Frequency Error XTAL Oscillator Input Voltage XTAL Oscillator Input Duty Cycle Reference Buffer Output Voltage Reference Buffer Output Duty Cycle Maximum REFOUT Pin Loading SYMBOL VCOspur CONDITIONS 0Hz < foffset < 10kHz 10kHz < foffset < 1MHz 1MHz < foffset < 10MHz XTALrge XTALerror XTALduty REFV Using an external XTAL (Note 8) Using an external TCXO Using the REFOUT pin loading specified below (Note 4) Using an external XTAL, not overdriven; bit RFD = 0, using the REFOUT pin loading specified below REFOUT pin frequency = 24MHz REFOUT pin frequency = 48MHz 24 -16 0.8 47 0.95 50 1.10 MIN TYP (Note 9) (Note 9) -47 49 +16 VCC 53 MHz ppm VP-P % VP-P dBc MAX UNITS
MAX2140
XTALswing Using an external TCXO
REFduty
45
50 20 8
55
%
REFOUT_1d
pF
TIMING CHARACTERISTICS
PARAMETER SERIAL INTERFACE (Note 2) Serial Clock Frequency fSCL 200 kHz SYMBOL CONDITIONS MIN TYP MAX UNITS
Note 1: Note 2: Note 3: Note 4: Note 5:
Note 6: Note 7: Note 8: Note 9:
At TA = -40C, minimum and maximum values are guaranteed by design and characterization. Minimum and maximum values are guaranteed by design and characterization, unless otherwise noted. At TA = +25C, minimum and maximum values are guaranteed by design and characterization. At TA = +25C and TA = +85C, parameters are production tested. IF AGC reference level is defined as being the required voltage applied on pin AGCPWM, and the corresponding receiver IF gain, to measure 20mVP-P at each I/Q differential output when the RF input power is -91dBm. If even for zero volts applied on pin AGCPWM the I/Q differential outputs are below 20mVP-P when the RF input power is -91dBm, then the reference level is defined as zero volts. In-band IP2 and IP3 are measured with two CW tones at RF input: f1 = 2339.55MHz, f2 = 2339.75MHz. Out-of-band IP2 and IP3 are measured with two CW tones at RF input: f1 = 2326.25MHz, f2 = 2330.25MHz. Error computed using a crystal with no error. No spur in the offset frequency range.
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Complete SDARS Receiver MAX2140
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
INPUT RETURN LOSS vs. FREQUENCY
MAX2140 toc01
RF AGC ENGAGEMENT THRESHOLD
MAX2140 toc02
RF AGC ATTENUATION vs. CONTROL VOLTAGE
MAX2140 toc03
0 -5 INPUT RETURN LOSS (dB) -10 -15 MAXIMUM RF AGC -20 -25 MINIMUM RF AGC -30 2.2 2.3 2.4
-10 RF AGC ENGAGEMENT THRESHOLD (dBm) -15 -20 -25 -30 DIVIDER: /8 -35 -40 DIVIDER: /4
60 50 RF AGC ATTENUATION (dB) 40 30 20 10 0 TA = +85C TA = -40C TA = +25C
2.5
0
4
8
12
16
20
0
0.6
1.2
1.8
2.4
3.0
FREQUENCY (GHz)
RF AGC ENGAGEMENT SETTING
CONTROL VOLTAGE (V)
RF AGC SETTLING TIME WITH 20dB STEP
MAX2140 toc04
IF AGC ATTENUATION vs. CONTROL VOLTAGE
MAX2140 toc05
IF AGC ATTENUATION vs. CONTROL VOLTAGE
R4 = 5000 C32 = 0.22F IF AGC ATTENUATION (dB) 40
MAX2140 toc06
0dBm RF AGC ATTACK TIME RF AGC DECAY TIME 5dB/div
70 60 IF AGC ATTENUATION (dB) 50 40 30 20
50
R4 = 100 C32 = 0.1F
TA = -40C TA = +85C TA = +25C
30 TA = -40C 20 TA = +85C TA = +25C
10
10 -50dBm START TIME: 0s STOP TIME: 200s 0 0 0.6 1.2 1.8 2.4 3.0 CONTROL VOLTAGE (V) 0 0 0.6 1.2
1.8
2.4
3.0
CONTROL VOLTAGE (V)
LPF FREQUENCY RESPONSE
MAX2140 toc07
0dB
10.250000MHz -27.278dB
-100dB 1MHz
16MHz
6
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Complete SDARS Receiver MAX2140
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
LPF GROUP DELAY vs. FREQUENCY
MAX2140 toc08
VCO PHASE NOISE vs. OFFSET FREQUENCY
MAX2140 toc09
REFOUT WAVEFORM (REF = 0, RFD = 0)
MAX2140 toc10
-50dBc/Hz
REF 80ns 100ns/div
6.250000MHz 113.8ns
500mV/div -150dBc/Hz 1MHz 16MHz 10 FREQUENCY OFFSET (Hz) 1M 20ns/div
REFOUT WAVEFORM (REF = 1, RFD = 0)
MAX2140 toc11
REFOUT WAVEFORM (REF = 1, RFD = 1)
MAX2140 toc12
200mV/div 10ns/div
500mV/div 20ns/div
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Complete SDARS Receiver MAX2140
Pin Description
PIN NAME VCC_FE0, VCC_FE1, VCC_FE2, VCC_BE1, VCC_BE2, VCC_BE3, VINANT, VCC_XTAL, VCC_D, VCC_A, VCC_FE3, VCC_VCO, VCC_BE4 RFIN+, RFINIFOUT+, IFOUTRFAGC_C AGCPWM IFIN+, IFINVOUTANT FUNCTION
1, 4, 8, 12-15, 23, 26, 27, 30, 31, 40
Power Supplies. Bypass to ground with capacitors as close to the pins as possible.
2, 3 5, 6 7 9 10, 11 16
Differential RF Inputs. Accept RF input signal from the SDARS cabled antenna with a 50 to 100 balun. Differential First IF Output. Connect an external SAW filter to the IF output. RF AGC Power-Detector Output. Set the RF AGC attack and decay response times. IF AGC Control Voltage Input. Input from the filtered PWM AGC control signal from the SDARS channel-decoder IC. Differential First IF Input Overcurrent-Protected Unregulated DC Supply Output. Provides DC power supply to the antenna module. Differential Baseband DC Blocking Outputs. IF2IO- = Inverting in-phase baseband output. AC couple to pin 18. IF2IO+ = Noninverting in-phase baseband output. AC couple to pin 20. IF2QO+ = Noninverting quadrature baseband output. AC couple to pin 36. IF2QO- = Inverting quadrature baseband output. AC couple to pin 38. Differential Baseband DC Blocking Inputs. IF2II- = Inverting in-phase baseband input. AC couple to pin 16. IF2II+ = Noninverting in-phase baseband input. AC couple to pin 19. IF2QI+ = Noninverting quadrature baseband input. AC couple to pin 37. IF2QI- = Inverting quadrature baseband input. AC couple to pin 39. Differential I/Q Baseband Outputs. IOUT- = Inverting in-phase baseband output. IOUT+ = Noninverting in-phase baseband output. QOUT+ = Noninverting quadrature baseband output. QOUT- = Inverting quadrature baseband output. Crystal Reference Input Buffered System Clock Output. Provides clock signal to the SDARS channel-decoder IC. Digital Logic Output to the System Controller. Indicates the lock status of the internal PLL. VCO Charge-Pump Output Regulated Supply Voltage for the VCO High-Impedance VCO Tuning Input I2C Input Signals. Define the MAX2140 I2C device address. I2C-Compatible Programming Input. Connect to an I2C-compatible bus. Exposed Paddle. Connect to ground.
17, 19, 37, 39
IF2IO-, IF2IO+, IF2QO+, IF2QO-
18, 20, 36, 38
IF2II-, IF2II+, IF2QI+, IF2QI-
21, 22, 34, 35 24 25 28 29 32 33 41, 42 43, 44 --
IOUT-, IOUT+, QOUT+, QOUTXTAL REFOUT LOCK CPOUT VCCREG VTUNE I2CA2, I2CA1 SCL, SDA Exposed Pad
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Complete SDARS Receiver
Detailed Description
Front End
The front end of the MAX2140, which downconverts the RF signal to IF, is defined from the differential RF inputs (pins RFIN+ and RFIN-) to the output (pins IFOUT+ and IFOUT-) to the SAW filter. The front end includes a self-contained analog RF AGC loop. The engagement threshold of the loop can be programmed from -35dBm to -15dBm referred to the RF input in 1dB steps using the RF4-RF0 programming bits. The time constant of the loop is set externally by the capacitor connected to RFAGC_C. The image reject first mixer ensures a good image and half IF rejection. The front-end gain can be reduced by programming bits PM3-PM0 over a 22dB range, with a step of 2dB. This allows the selections of SAW filters with different insertion loss. The IF output is nominally 900 differentially and requires pullup inductors to VCC, which can be used as part of the matching network to the SAW filter impedance. IF2 access pins, given by the following equation: fcutoff = 1/(2 x x R x C) [Hz] where R = 8000, C = external capacitor to be connected. Finally, the HPF bit allows an increase to the back-end gain by 4dB at the slight expense of a degraded inband linearity.
MAX2140
Frequency Generation
An on-chip VCO and a low-step fractional-N PLL ensure the necessary frequency generation. The 1st mixer's LO is at the VCO frequency itself, while the 2nd mixer's LO is the VCO frequency divided by 4 or by 8 (bit D48). Hence, the two possible IF frequencies for SDARS are 467MHz and 259MHz. Typical applications are based on 259MHz IF frequency. The reference divider path in the PLL can either use an external crystal and the on-chip crystal oscillator or an external TCXO that can overdrive the on-chip crystal oscillator. A reference division ratio of 1 or 2 is set by the REF bit. The crystal oscillator (or TCXO) signal is available at pin REFOUT. The output is either at the same frequency as the reference signal, or divided by two, based on the setting of bit RFD. The VCO main division ratio is set by bits N6-N0 (for the integer part) and bits F19-F00 (for the fractional part). The minimum step is below 30Hz, small enough for effective AFC to be implemented by the baseband. The charge-pump (pin CPOUT) is to be connected to the VCO tuning input (pin VTUNE) through an appropriate loop filter.
Back End
The back end, which downconverts the IF signal to quadrature baseband, is defined from the SAW filter inputs (pins IFIN+ and IFIN-) to the baseband outputs (pins IOUT+, IOUT-, QOUT+, QOUT-). The back end contains an IF AGC loop, which is closed by the baseband controller. The IF AGC control voltage is applied at the AGCPWM pin. The gain can be reduced over 53dB (typ) and exhibits a log-linear characteristic. The back end also contains individual lowpass filters on each channel. The lowpass-filter bandwidth is the useful SDARS downconverted bandwidth (6.25MHz). The lowpass-filter performance is factory trimmed. The bit IOT switches between the factory-trimmed set and the control through the I 2 C-compatible bus using bits B4-B1. Even when using the factory-trimmed set, the user can still slightly modify the cutoff frequency (by 250kHz) by varying bits LP1/LP0. Highpass filters are also inserted in the back-end signal paths. Their purpose is to remove the DC offset. They are designed for a low corner frequency so as not to degrade the SDARS content. Their exact cutoff frequency is set by the external capacitors connected between
Overcurrent Protection
This DC function allows external circuitry consuming up to 150mA and connected to the pin VOUTANT to sink current from a VCC line (pin VINANT) through overcurrent-protection circuitry. When no overcurrent is present, a low dropout voltage exists between pins VINANT and VOUTANT. In overcurrent conditions (including short-circuit from VOUTANT to GND), the current is limited to approximately 300mA and bit ACP in the READ byte status goes high. This circuit also senses if the current drawn at the pin VOUTANT is typically larger than 20mA, in which case the bit AND from the READ byte status goes high (the purpose is to inform the baseband controller if there is any device drawing current from VOUTANT).
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Complete SDARS Receiver MAX2140
Applications Information
Serial Interface and Control Registers
I 2C Bit Description MAX2140 Programming Bits: The MAX2140 conforms to the Philips I 2C standard, 400kbps (fast mode), and operates as a slave. The MAX2140 addresses can be selected from three values, which are determined by the logic state of the two address-select pins I2CA1 and I2CA2. In all cases, the MSB is transmitted (and read) first. MAX2140 I2C-Compatible Programming Bit Definition: BYTE PLLint: RFD = reference buffer division: RFD = 0 (/1) and RFD = 1 (/2) N6 to N0 is the binary-written main dividing ratio, integer part. BYTE PLLfrac2: PLS = Reserved: use only PLS = 0 LI1/0 = Reserved: use only LI1 = LI0 = 0 INT = Integer N mode: INT = 1 (fractional) and INT = 0 (integer)
Table 1. MAX2140 Write Address Bytes
AS1 Low High High AS0 High Low High MSB 1 1 1 1 1 1 0 0 0 ADDRESS BYTE 0 0 0 0 0 0 0 1 1 1 0 1 LSB 0 0 0
Table 2. MAX2140 Read Address Bytes
AS1 Low High High AS0 High Low High MSB 1 1 1 1 1 1 0 0 0 ADDRESS BYTE 0 0 0 0 0 0 0 1 1 1 0 1 LSB 1 1 1
Table 3. MAX2140 Write Programming Bits
WRITE-TO MODE Address PLLint PLLfrac2 PLLfrac1 PLLfrac0 Control CustomGain PMA_Test LPFTrim Unused2 Unused1 Unused0 RESET VALUE -- 01010110 00011110 10010000 01101001 01100000 00000100 00000000 00000000 00000000 00000000 00000000 ADDR (hex) C2 C4 C6 00 01 02 03 04 05 06 09 08 07 10 MSB 1 1 1 RFD PLS F15 F07 REF RF4 PM3 0 0 0 0 1 1 1 N6 LI1 F14 F06 CHP RF3 PM2 0 0 0 0 0 0 0 N5 LI0 F13 F05 D48 RF2 PM1 IOT 0 0 0 CONTROL BYTE 0 0 0 N4 INT F12 F04 SDR RF1 PM0 B4 0 0 0 0 0 0 N3 F19 F11 F03 ANT RF0 SDX B3 0 0 0 0 1 1 N2 F18 F10 F02 SDF LP1 T2 B2A 0 0 0 1 0 1 N1 F17 F09 F01 SDB LP0 T1 B2 0 0 0 LSB 0 0 0 N0 F16 F08 F00 SDP HPF T0 B1 0 0 0
10
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Complete SDARS Receiver
F19 to F16 is the upper-part binary-written main dividing ratio, fractional part multiplied by 2 20 = 1,048,576. BYTES PLLfrac1 and PLLfrac0: F15 to F0 is the lower-part binary-written main dividing ratio, fractional part multiplied by 220 = 1,048,576. BYTE Control: REF = reference division ratio: REF = 0 (/1) and REF = 1 (/2) CHP = charge-pump current: CHP = 0 (0.6mA) and CHP = 1 (1.2mA) D48 = LO division ratio: D48 = 0 (/4) and D48 = 1 (/8) SDR = shutdown RF AGC: SDR = 0 (on) and SDR = 1 (shutdown) ANT = antenna overcurrent protection: ANT = 0 (on) and ANT = 1 (shutdown) SDF = shutdown front end: SDF = 0 (on) and SDF = 1 (shutdown) SDB = shutdown back end: SDB = 0 (on) and SDB = 1 (shutdown) SDP = shutdown PLL: SDP = 0 (on) and SDP = 1 (shutdown) BYTE CustomGain: RF4/RF3/RF2/RF1/RF0 = RF AGC engagement threshold (dBm): see the RF AGC Settling Time graph in the Typical Operating Characteristics. LP1/LP0 = change by 250kHz the LPF corner frequency: LP1/LP0 = 10 (nominal), LP1/LP0 = 11 (decrease), LP1/LP0 = 00 (increase) HPF = HPF gain increase by 4dB: HPF = 0 (off) and HPF = 1 (on) BYTE PMA_Test: PM3/PM2/PM1/PM0 = PMA gain cutback (dB): PM3/PM2/PM1/PM0DEC SDX = shutdown reference buffer: SDX = 0 (on) and SDX = 1 (shutdown) T2/T1/T0 = test bits: 000 (normal), 001 (main division), 010 (reference division), 011 (reserved), 100 (CHP low-Z), 101 (CHP source on), 110 (CHP sink on), 111 (CHP high-Z) BYTE LPFTrim: B4/B3/B2/B2A/B1 = Reserved for LPF trim. All = 0 in normal operating mode IOT = LPF corner frequency setup: IOT = 0 (default factory trim) and IOT = 1 (controllable through I2C). IOT = 0 in normal operating mode BYTE Status: RF AGC = RF AGC status: RF AGC = 0 (is not engaged) and RF AGC = 1 (engaged) ACP = antenna current protection: ACP = 0 (no overcurrent) and ACP = 1 (overcurrent) AND = antenna detection: ANT = 0 (current < threshold) and ANT = 1 (current > threshold) LD = lock detect: LD = 0 (out of lock) and LD = 1 (lock) BYTE Reserved: Inactive at this time, all bits are 0 Register configuration for the LO generation when the comparison frequency = 23.92MHz: to generate 2078.893333MHz: PLLint = 01010110, PLLfrac2 = 00011110, PLLfrac1= 10010000, PLLfrac0 = 01101001 to generate 2067.777778MHz: PLLint = 01010110, PLLfrac2 = 00010111, PLLfrac1 = 00100001, PLLfrac0 = 00000010 to generate 1871.004000 MHz: PLLint = 01001110, PLLfrac2 = 00010011, PLLfrac1 = 10000001, PLLfrac0 = 11111000 to generate 1861.000000MHz: PLLint = 01001101, PLLfrac2 = 00011100, PLLfrac1 = 11010000, PLLfrac0 = 11101000
MAX2140
Table 4. MAX2140 Read Programming Bits
READ-FROM MODE Address Reserved Status RESET VALUE -- 00000000 00000000 ADDRESS (hex) C3 C5 C7 00 01 MSB 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0 CONTROL BYTE 0 0 0 0 0 0 0 0 0 RFAGC 0 1 1 0 ACP 1 0 1 0 AND LSB 1 1 1 0 LD
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11
Complete SDARS Receiver
I 2C Functional Description I2C Register Map: This is the standard I2C protocol. The first byte is either C6, C4, C2 (hex) dependent on the state of the I2CA_ pins, for a write-to-device operation and either C7, C5, C3 (hex) for a read-from operation (again dependent on the state of pins I2CA_). Write Operation: The first byte is the device address plus the direction bit (R/W = 0). The second byte contains the internal address command of the first address to be accessed. The third byte is written to the internal register directed by the command address byte. The following bytes (if any) are written into successive internal registers. The transfer lasts until stop conditions are encountered. The MAX2140 acknowledges every byte transfer. Read Operation: When either address C3, C5, C7 is sent, the MAX2140 sends back first the status byte then the reserved byte. See Table 5 and Table 6 for read/write register operations.
MAX2140
Power-Supply Layout
To minimize coupling between different sections of the IC, the ideal power-supply layout is a star configuration, which has a large decoupling capacitor at a central VCC node. The VCC traces branch out from this node, each going to a separate VCC node in the MAX2140 circuit. At the end of each trace is a bypass capacitor with impedance to ground less than 1 at the frequency of interest. This arrangement provides local decoupling at each VCC pin. Use at least one via per bypass capacitor for a low-inductance ground connection.
Matching Network Layout
The layout of a matching network can be very sensitive to parasitic circuit elements. To minimize parasitic inductance, keep all traces short and place components as close to the IC as possible. To minimize parasitic capacitance, a cutout in the ground plane (and any other planes) below the matching network components can be used. On the high-impedance ports (e.g., IF inputs and outputs), keep traces short to minimize shunt capacitance.
Chip Information
TRANSISTOR COUNT: 22,000 PROCESS: BiCMOS
Layout Issues
The MAX2140 EV kit can be used as a starting point for layout. For best performance, take into consideration power-supply issues, as well as the RF, LO, and IF layout.
Table 5. Example: Write Registers 1 to 3 with 0E, D8, 26
Device Address Write (C2, C4, C6) ACK Register Address 00 ACK DATA 0E ACK DATA D8 ACK DATA 26 ACK STOP
Table 6. Example: Read from Status Registers (Sending an NACK Terminate Slave Transmit Mode
Start Device Address Read (C1, C3, C5, C7) ACK Status Register 00 ACK/\NACK STOP
Package Information
For the latest package outline information, go to www.maxim-ic.com/packages.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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